A storage device is configured by a controller group and a drive group, and manages a plurality of physical devices by RAID (Redundant Array of Independent/Inexpensive Disks). The controller group is the one controlling input/output of data to/from the storage device, and the drive group is the one configured by a plurality of physical devices for storage of the data. These physical devices offer a physical storage area, on which at least one or more logic volumes (hereinafter, referred to as logic devices) are formed.
In the controller group, a shared memory for use of temporary data storage is often configured separately from a plurality of microprocessors in charge of control over data input/output. The microprocessors are each connected with a local memory storing a storage-device operating program to be run by the microprocessors, control information, and others. With such a configuration, however, the time taken for the microprocessors to access the shared memory is longer than the time taken to access the local memory, i.e., several to several hundred times longer. Another concern is the shared use of the shared memory by the microprocessors, and for data input/output by the microprocessors, any of the microprocessors making access to the shared memory has to lock, access, and unlock the shared memory to prevent the remaining microprocessors from making access to the shared memory. If a plurality of microprocessors use the same shared memory as such, the processing time of making access to the shared memory takes very long.
In consideration thereof, Patent Document 1 (JP-A-2005-267545) describes a technology for reducing the frequency of accessing the shared memory. To be specific, in a storage device incorporated with a controller group in which a shared memory is configured separately from a plurality of microprocessors, the controller group makes an assignment of ownership to any selected microprocessor. After such an assignment of ownership, only the microprocessor assigned the ownership is allowed to perform the processing of data input/output with respect to an arbitrary logic device. Moreover, accessing information of the arbitrary logic device stored in the share memory is also allowed only to the microprocessor assigned the ownership. As such, because only any selected microprocessor is allowed to access information of an arbitrary logic device, if such information is once acquired from the shared memory for storage on the local memory, the shared memory is not necessarily accessed again.
With the technology of Patent Document 1, considering only the load conditions of an arbitrary logic device to be processed by the ownership-assigned microprocessor, the controller group is in charge of ownership transfer. That is, no consideration is given to the correlation among various factors related to the storage device, e.g., the correlation between the arbitrary logic device and any other logic devices, and the correlation between the processing of data input/output and any other processing. As a result, for the control group to transfer the ownership of the arbitrary logic device, communications take time between the ownership-transfer-source microprocessor to an ownership-transfer-destination microprocessor, and thus the load to be imposed on these microprocessors is instead increased. This thus causes a problem that, although the storage device is incorporated with a plurality of microprocessors for the purpose of high-speed processing, the performance capabilities thereof are instead reduced.